Among the requirements of variety of microelectronic circuit components and systems is the need for the circuit-containing modules to have a high packing density (minimum volume). For this purpose, the integrated circuit chip packaging industry has developed a number of multi-chip assembly architectures through which a plurality of leadless chip carriers (LCCs) or a plurality of semiconductor (silicon) dies may be mounted in a `stacked` configuration on a printed wiring board and interconnected by means of pad-to-pad bonds between die-containing elements.
An example of such a stacked packaging assembly is diagrammatically illustrated in FIG. 1, which shows a plurality of (e.g. six) chip-carrying `tubs` 11-1 . . . 11-6 having upper or topside surfaces 13-1 . . . 13-6 and lower or bottomside surfaces 15-1 . . . 15-6, respectively, around the periphery of which respective pluralities of bonding pads 21-1 . . . 21-6 and 23-1 . . . 23-6 are distributed. A respective tub may be formed of a lamination of multiple, very thin layers of low temperature co-fired ceramic (LTCC) material, which are capable of being hermetically sealed.
An individual tub 11 has a floor portion 12 upon which a semiconductor circuit chip (die) 31 is mounted, and a surrounding wall portion 14, which is adjacent to and defines the perimeter of the floor portion. The floor portion of the tub may be formed of a bottom one of the laminate of LTCC layers, the bottom surface of which forms the bottom surface of the tub 11, proper. A generally centrally located region 32 of the top surface of the adjacent floor layer forms the mounting surface for a semiconductor circuit chip 31. As a non-limiting example, the die may be mechanically secured to the top surface of the floor portion by means of non-organic silver/glass die attachment material.
The terminal pads of a respective die 31 are typically distributed around the periphery of its top surface for connection through a lead distribution network to bonding pads 21 and 23 through which external access to the chip is provided. The bond pads 21 on the upper surface 13 of the surrounding wall portion of a respective tub 11 are customarily spatially vertically aligned with the bonding pads 23 on the lower surface 15 of that tub, and conductively filled or plated through vias 25 are formed in the tub, so as to provide a top-to-bottom interconnect path for each tub.
In order to connect one or more pads to the circuitry of a respective semiconductor die or chip 31, that is disposed on floor portion 12 of the interior of a tub 11, the layer of metal of which the (upper) bonding pads 21 are formed may be patterned to provide a pad extension layer, such as that shown at 41. The geometry of the pad extension layer 41 is configured to allow a relatively linear connection of a chip interconnect lead 43, from a lip or edge portion 45 of one of the layers of the laminate structure of the tub to a via 51 that is vertically aligned with a portion of the pad extension layer 41. Connections to the circuitry of the chip proper are provided by respective leads 53 that join interconnect leads 43 to contact regions 55 on the chip.
As one proceeds through the stack of tubs, a respectively different one of the upper bonding pads 21 has an associated pad extension layer 41, so as to allow a different one of chip connection leads 53 to be joined to a respectively different upper pad 21. Since the upper pads are spatially aligned with the lower pads 23, then, as diagrammatically illustrated in FIG. 2, with the tubs stacked together and pad-to-pad bonds provided between opposing tubs, it can be seen that a plurality of vertical interconnect paths 61-1 . . . 61-6 are provided through successively interconnected through vias 25 of the stack of tubs, thereby providing external electrical access, via pads 23 of the lowermost tub 11-1, to each of the chips mounted within the stack of tubs.
Now, although the tub architecture and associated bonding pad sites of the conventional stacked packaging assembly of FIGS. 1 and 2 allows a plurality of leadless chip carriers or tub-housed semiconductor dies to be arranged in a `stacked` configuration on a printed wiring board and interconnected by means of pad-to-pad bonds between tubs, each tub in the stack must employ a respectively different pad extension layer pattern. As a consequence, as the number of tubs in the stack increases there is an associated need for an increased number of different tub designs, which not only increases cost of manufacture, but makes the yield of the overall multi-tub packaging assembly dependent upon the yield of its lowest yield tub. Moreover, because each tub is unique, the tubs are not interchangeable.